The present invention relates to a semiconductor device and a manufacturing method thereof, and can be suitably applied to a semiconductor device including, for example, a split gate type nonvolatile memory cell.
In a semiconductor device in which a nonvolatile memory is mounted, a memory cell region and a peripheral circuit region are defined in a semiconductor substrate. In the memory cell region, a memory cell is formed. In the peripheral circuit region, a predetermined semiconductor element including, for example, a MIS transistor (MISFET: Metal Insulator Semiconductor Field Effect Transistor) is formed.
A nonvolatile memory cell includes a split gate type memory cell to which a MONOS (Metal Oxide Nitride Oxide Semiconductor) film is applied. The memory cell is formed by two MIS transistors including a control transistor and a memory transistor. The control transistor has a control gate electrode. The memory transistor has a memory gate electrode. The memory gate electrode is formed over the side surface of the control gate electrode via an insulating film. The memory gate electrode is formed by leaving a conductive film in the form of a sidewall spacer.
The patent documents disclosing such a nonvolatile memory include, for example, Patent Documents 1 and 2. Patent Document 1 proposes a technique in which after a control gate electrode and a memory gate electrode are formed in a memory cell region, the gate electrode of a MIS transistor is formed in a peripheral circuit region. Patent Document 2 proposes a technique in which after a control gate electrode and a memory gate electrode are formed in a memory cell region and after the dummy gate electrode of a MIS transistor is formed in a peripheral circuit region, an original gate electrode is formed by removing the dummy gate electrode.
Semiconductor devices are generally shrunk according to the scaling thereof. In particular, in an MIS transistor, current driving force decreases when a channel width becomes small. In order to secure a channel width, Patent Document 3 proposes a technique in which an active region where a memory cell is to be formed is allowed to have a convex shape such that the side surface of the convex active region is used as a channel.
In particular, in a semiconductor device including a memory cell region and a peripheral circuit region, the effective channel width of each of a control transistor and a memory transistor is secured by lowering the height of an element isolation insulating film defining the memory cell region (memory active region) than that of an element isolation insulating film defining the peripheral circuit region (peripheral active region).